**RAM** (Random Access Memory) Memory that can be accessed and written to randomly (by address location). The Northbridge/Memory Controller Hub coordinate these functions. * **SRAM** (Static RAM) * Used for cache * Faster than DRAM, more expensive * Takes more physical space (each bit requires 6 or more transistors) * Does not need refreshing * **DRAM** (Dynamic RAM) * Used for main memory * Slower than SRAM, less expensive * Needs periodic refreshing (leaky capacitors) * **SDRAM** (Synchronous DRAM) * The memory bus is synchronized with the front-side bus * **RDRAM** (Rambus DRAM) * Proprietary RAM architecture * 16 or 32 bit bus widths * Not used much anymore * **DDR SDRAM** (Double Data Rate SDRAM) * Data is transmitted on both the rising and falling edge of the clock cycle * Doubles the memory throughput of basic SDRAM * 2-bit Prefetch * **DDR2 SDRAM** * Uses "double pumping" like DDR but has a faster I/O bus * Theoretical memory throughput quadruples basic SDRAM * Typically has a higher CAS latency than regular DDR (slower access time by the memory controller hub and more CPU cycles pass before getting the data) * Uses less power than DDR modules * 4-bit Prefetch * **Parity RAM** * An additional bit is added for every byte of data stored in RAM. Basic comparison tests can be done with these extra bits to determine if a sequence of bytes are bad or not. * Can only detect errors, not correct them. * CAS Latency (CL) is generally worse than non-parity RAM * Not really used anymore * **Error Correcting Code (ECC) RAM** * Uses codes to test and fix errors * Can correct memory errors on the fly * CAS Latency (CL) is generally worse than non-ECC RAM * ECC memory is more expensive * Typically found in workstations and servers. * **Registered Memory** * Additional memory chips are added to act as a buffer * The buffer regulates data traffic flow over the memory bus * More expensive than non-buffered RAM modules * Typically found in workstations and servers * **Dual-Channel** * The Northbridge/Memory controller hub uses two data channels to transmit data * The theoretical throughput is doubled on top of what DDR or DDR2 modules might provide * Matching pairs must occupy memory slots for this architecture to provide any bandwidth benefits \\ **ROM** (Read-only Memory) Memory that can be read only. The term is a bit misleading in that all but one type of ROM permits some sort of additional writing. * **ROM** - Can only be read and not written to except by the manufacturer of the chip. * **PROM** (Programmable ROM) - Can be written to once. * **EPROM** (Erasable Programmable ROM) - Can be written to and erased using UV light. * **EEPROM** (Electrically Erasable Programmable ROM) - Can be written to and erased electrically. This type of ROM is also known as Flash memory.