The chipset comprises of two chips on typical PC architecture. The chipset's accompanying chips are the central hubs/bridges that all buses of different capacities connect to. The chipset is responsible for the majority of the motherboard's controller functions and connecting the CPU to memory and all other devices on the motherboard. Both chips are interconnected by a high-bandwidth bus called the Internal Bus.

Northbridge (AMD, Via, SiS) or Memory Controller Hub (Intel)

• The basic Northbridge is a controller which controls the flow of data between the CPU and RAM, and to the AGP graphics bus or PCI Express serial bus (lanes). When for example, the CPU requests data from a specific address in RAM, it calls on the Northbridge/MCH to find the RAM module with address and access the contents. The operating system may control via drivers how it manages these tasks to, for example, prevent dangerous instructions from reading and/or writing to allocated memory addresses.

Southbridge (AMD, Via, SiS) or I/O Controller Hub (Intel)

• The Southbridge or I/O Controller Hub has many controller functions built into the chip; these functions might include hard drive, floppy, sound, Ethernet, wireless, and even graphics controllers. Each of these controllers need corresponding drivers in order for the operating system to access and communicate with them. The Southbridge/ICH also connects all the slower I/O buses (PCI, EISA, ISA, VLB, PATA, SATA) together to enable communication across the various expansion slots, drive connectors, and ROM BIOS.

Super I/O

• A hub/bridge similar to that of the Southbridge or I/O Controller Hub in that it has many controller functions. Unlike the Southbridge or I/O Controller Hub the Super I/O manages data transmission to very-low bandwidth devices, such as the floppy drive and I/O ports: DIN, PS/2, serial, parallel, gameport.
• Connects to the Southbridge or I/O Controller Hub via a low-bandwidth bus known as Low Pin Count (LPC) bus.